Aspects of semiconductor technology have focused on providing a semiconductor device capable of embodying a high-capacitance capacitor in a logic circuit requiring a high-speed operation.
The high-capacitance capacitor may be classified as a metal-insulator-metal (MIM) capacitor or a polysilicon-insulator-polysilicon (PIP) capacitor. Unlike a metal oxide silicon (MOS) capacitor or a junction capacitor, MIM capacitors and PIP capacitors are bias independent, and therefore, requires accuracy.
Specifically, the MIM capacitor may be fabricated simultaneously with the formation of metal lines during a semiconductor process. Consequently, an additional metal process may be required after the fabrication of the semiconductor device. On the other hand, the PIP capacitor may be fabricated on and/or over a shallow trench isolation (STI) layer, with the result that an additional process is not required unlike the MIM capacitor. Also, the PIP capacitor may be widely used for noise prevention and frequency modulation of an analog device. Moreover, a bottom electrode and a top electrode of the PIP capacitor may be composed of the same material such as polysilicon, as a gate electrode material of a logic transistor. Consequently, the electrodes of the PIP capacitor are fabricated simultaneously with the fabrication of a gate electrode without the provision of an additional process.
As illustrated in example FIG. 1A, a method of fabricating a PIP capacitor in a semiconductor device may include forming shallow trench isolation (STI) layer 12 on and/or over silicon semiconductor substrate 10 through an isolation process. Accordingly, semiconductor substrate 10 is divided into an active area and an isolation area. The active area may then be ion-implanted with a dopant, which is necessary for controlling a threshold voltage, through an ion implantation process.
An insulation layer may then be deposited on and/or over the entire surface of the active area of semiconductor substrate 10. A first polysilicon layer, which may be used as a gate electrode of a logic transistor and a bottom electrode of a PIP capacitor, may then be deposited on and/or over the insulation layer. A photolithographic and dry etching process using a mask for bottom electrode 18 of the capacitor may then be carried out to pattern the first polysilicone layer such that bottom electrode 18 of the capacitor is formed on and/or over STI layer 12. An ion implantation process may then be carried out to increase the dopant concentration of bottom electrode 18.
An oxide-nitride-oxide (ONO) layer, as dielectric layer 20, may then be deposited on and/or over the entire surface of the structure. A second polysilicone layer, which will be used as a top electrode of the PIP capacitor, may then be deposited and ion-implanted on and/or over the ONO layer. Photolithographic and dry etching processes using masks for the gate electrode of the logic transistor and the top electrode of the capacitor may then be carried out to pattern the second polysilicone layer, located on and/or over STI layer 12 to form top electrode 22 of the capacitor on and/or over dielectric layer 20 and also pattern dielectric layer 20 located below top electrode 22. At the same time, the second polysilicone layer may be patterned on the active area of semiconductor substrate 10 to form gate electrode 16 of the logic transistor. The insulation layer, provided below gate electrode 16, may also be patterned to form gate insulation layer 14.
Subsequently, a lightly doped drain (LDD) ion implantation process is carried out on the active area of the logic transistor to form n-type LDD or p-type LDD regions in semiconductor substrate 10. The n-type LDD or p-type LDD regions may be spaced apart from each other by the width of gate electrode 16.
As illustrated in example FIG. 1B, an insulation layer composed of silicon nitride (Si3N4) may then be deposited on and/or over the entire surface of the structure. The silicon nitride layer may then be dry-etched to form spacers 24 at opposite sidewalls of top electrode 22, dielectric layer 20 and bottom electrode 18 of the capacitor. Spacers 24 may also be formed at opposite sidewalls of gate insulation layer 14 and gate electrode 16 of the logic transistor. Subsequently, a source/drain ion implantation process may then be carried out on the logic transistor area to form source/drain areas 26 in semiconductor substrate 10. Source/drain areas 26 may be spaced apart from each other by the width of gate electrode 16 and spacers 24.
As illustrated in example FIG. 1C, blocking oxide layer 28 may then be formed on and/or over the surface of top electrode 22 of the capacitor or a position of the logic transistor area where a silicide metal layer will not be formed. Subsequently, a silicide metal layer composed of titanium (Ti) may then be deposited on and/or over the entire surface of semiconductor substrate 10. The titanium layer may then be annealed to form first titanium silicide layer 30a and second titanium silicide layer 30b. Specifically, first titanium silicide layer 30a may be formed on and/or over the surface of gate electrode 16 or source/drain area 26 of the logic transistor. Second titanium silicide layer 30b may be formed on and/or over the surface of bottom electrode 18 of the capacitor.
As illustrated in example FIG. 1D, etching stop layer 32 composed of silicon nitride may then be formed on and/or over the entire surface of the structure. Poly metal dielectric (PMD) layer 34 composed of borophosphoric silicate glass (BPSG) or phospho silicate glass (PSG) may then be deposited and annealed on and/or over etching stop layer 32. Subsequently, a chemical mechanical polishing (CMP) process may then be carried out to planarize the surface of poly metal dielectric layer 34. Buffer oxide layer 36 may then be formed on and/or over poly metal dielectric layer 34 to compensate for scratches generated during the CMP process.
As illustrated in example FIG. 1E, a photolithographic process using a mask for a top electrode contact hole of the capacitor may then be carried out on buffer oxide layer 36 to form a photoresist pattern defining a contact hole area of the capacitor. Subsequently, buffer oxide layer 36 and blocking oxide layer 28, including the layers disposed therebetween, may then be etched through a dry etching process to form contact hole 38 to expose the uppermost surface of top electrode 22 of the capacitor. The photoresist pattern may then be removed.
As illustrated in example FIG. 1F, a photolithographic process using a mask for bottom electrode contact holes of the capacitor and contact holes of the logic transistor may then be carried out on buffer oxide layer 36 to form a photoresist pattern defining a contact hole area of the logic transistor and a bottom electrode contact hole area of the capacitor. Subsequently, buffer oxide layer 36 and etching stop layer 32, including the layer disposed therebetween, may then be etched through a dry etching process to form contact holes 40 to expose the uppermost surface of gate electrode 16 of the logic transistor or the uppermost surface of first silicide layer 30a of source/drain area 26. At the same time, contact hole 40 may be formed to expose the uppermost surface of second silicide layer 30b of bottom electrode 18 of the capacitor.
As illustrated in example FIG. 1G, contact holes 38 and contact holes 40, extending from buffer oxide layer 36 to etching stop layer 32, may then be filled with a conductive layer such as doped polysilicone or a metal material. The conductive layer may then be patterned to form contacts 42 electrically connected to gate electrode 16 of the transistor and source/drain area 26 and also contacts 44 electrically connected to bottom electrode 18 and top electrode 22 of the capacitor. Subsequently, line 46 may then be formed on and/or over buffer oxide layer 36 for connection to contacts 42 and contacts 44.
In accordance with the aforelisted method of fabricating a PIP capacitor in a semiconductor device, however, the PIP capacitor is constructed in a structure having two stacked polysilicon layers. Accordingly, the contact hole etching process must be carried out twice due to the difference in height between the logic transistor and the capacitor. This complicates the fabrication process and increases fabrication costs.
Furthermore, the oxide capacitor and the PIP capacitor cannot be simultaneously used, although the capacitor may be formed using the PIP. Consequently, the capacity of the capacitor is excessively limited.